The present invention relates generally to an interface circuit connected between a processing component and a sensor. More specifically, the invention relates to an interface circuit that translates sensor voltages outside the voltage range of the power supply voltage of the processing component into voltages within range of the power supply voltage of the processing component.
Sensors, particularly in automotive applications, produce varying output voltages corresponding to particular sensed characteristics. The output of a sensor usually requires signal processing such as noise filtering and analog-to-digital conversion, for example. Signal processing circuits commonly use CMOS components having a zero to five volt power supply. It is common for sensors to produce an output voltage exceeding the range of the power supply of the CMOS circuitry. Voltages exceeding the power supply voltage result in an inaccurate measurement. Consequently, some interface circuit is required to translate the sensor voltage within the range of the power supply.
Previous voltage translation circuits use a MOS type transistor to perform switching of the sensor output voltages across a pair of capacitors according to a clock signal. This type of circuit is known as a switched capacitor circuit. However, this voltage translation circuitry does not take into account high voltages which may be developed at the switch. MOS type transistors have a gate terminal which is isolated from a drain terminal, a source terminal and bulk terminal by a gate oxide layer. The gate oxide layer must be thick enough to withstand excessive voltage potentials generated during the switching of the transistor. Sudden failure of the transistor due to extremely excessive voltages is an eventuality that must be taken into account by the design. Time dependent dielectric breakdown (TDDB) is another type of failure that occurs when the MOS type transistor breaks down over time due to the stress of excessive voltages across the gate oxide layer. The gate oxide layer of prior designs is formed thick enough (e.g., at least 250 angstroms thick) to withstand the relatively high voltage potentials developed during switching.
CMOS processes have been developed using thinner gate oxide thickness (e.g., 150 angstroms or less). Components using reduced oxide gate thickness are cheaper to manufacture, have faster switching times and have a smaller package size, all of which are desirable in integrated circuit designs. Previous voltage translation circuits generate high gate oxide voltages which would cause TDDB if thinner CMOS gate oxides were used.
It would therefore be desirable to incorporate thinner oxide layer MOSFETs into voltage translation circuitry without compromising the reliability of the circuitry.